In nanometer process geometries, issues relating to timing, signal integrity, manufacturing and time to market are presenting new challenges to designers and EDA tools. Timing is interconnects dominated. In 130 nm designs, for example, interconnect delay accounts for about 80% of the path delay, while coupling capacitance accounts for approximately 70% of the total wire capacitance. Crosstalk, which is the most common and severe signal integrity problem, may cause induced glitches and timing errors. Timing constraints are generally managed during floor planning by controlling interconnect length, and by sizing cells. Crosstalk constraints on the other hand, may only be addressed once the absolute positions of the interconnecting wires are known, generally after routing is determined. Crosstalk is an electrical phenomenon that may occur when spatial correlations between the interconnecting wires exist or, in other words, when the geometry of the interconnecting wires is arranged in specific configurations that cause coupling capacitance to increase dramatically. Crosstalk makes a-priori prediction of timing closure difficult or impossible.
Crosstalk is generally managed by upsizing drivers for setup-time violations, inserting buffers for hold-time violations, shielding critical nets, and controlling spacing and parallelism. However, there is no way to optimally trade-off between resizing cells and fine-tuning the coupling capacitances, forcing designers to use either method, or both, in brute force.
Power consumption has been growing exponentially with each process generation. In 90 nm process geometry for example, leakage power contributes approximately half of the total power budget, with active power dissipation from device switching making up the rest. Fixing crosstalk by upsizing cells and inserting delay cells makes a bad situation worse with respect to power. Therefore, power is managed by reducing voltages, leading to a greater sensitivity to rail voltage variations and smaller margins for switching noise. As coupling capacitances continue to increase, so does the switching noise—which is a direct result of the ever-shrinking process geometries. The dramatic increase of the coupling capacitances in nanometer technology is making a-priori prediction of timing closure early in the design process, and a first pass design success “almost” impossible—a vicious circle has been created.
At 180 nm and below, aggressive resolution enhancement techniques (RET) are typically employed in order to assure that the resulting silicon pattern will match the layout exactly. Nevertheless, the ability to apply RET effectively is limited by the layout itself. To follow best practices for example, designs are required to meet minimum design rules—spacing rules, reliability rules (via stacking and minimum area rules), and process antennas rules, making RET difficult to apply. When design rules are relaxed from the minimum specifications in selected areas of the chip, RET is easier to apply, resulting in an overall yield increase without dramatically affecting design size or functionality.
Ideally, crosstalk, power and yield problems should be managed by minimizing the coupling capacitances between the interconnecting wires. It is well known that for a given area constraint, performance driven wire-spacing optimization is the most effective method for reducing interconnect coupling capacitances, reducing power, and increasing yield. Optimization based on a tradeoff between fine-tuning the coupling capacitances and resizing cells, in conjunction with buffer insertion may be the most effective method yet. Wire-spacing techniques hold the key to addressing the impact of geometrical constraints on parasitic, timing, power, and yield.
Wire-spacing techniques rely on compaction and spacing. Because compaction is a 2-D NP-complete problem it is extremely difficult to solve. As a result two 1-D problems are typically solved; X followed by Y or vice versa. Unfortunately, minimizing crosstalk between horizontal segments may maximize crosstalk between vertical segments, resulting in a redistribution of the problem. Therefore, there is no trivial way to automatically control spacing and parallelism, which are both critical to minimizing the coupling capacitances.
Ameliorating crosstalk noise during routing implies prescience because knowledge of the expected crosstalk due to nets that are not yet routed is needed in order characterize and attempt to minimize crosstalk. During global routing, crosstalk estimation may be inaccurate, but the freedom to control crosstalk is nearly unrestricted. On the other hand, during detail routing, crosstalk estimation may be more accurate, but the freedom to control crosstalk is more restricted. Therefore, routers attempt to constrain the routing by meeting not only manufacturing rules, but also meeting blanket-rule constraints for net parallelism and spacing, needed for crosstalk control. The blanket application of net parallelism and spacing rules may over-design crosstalk for some nets, while under-design crosstalk for others. When routing is over-constrained, irresolvable congestion problems often occur making it difficult to achieve 100% routing completion. As a result, worse case rules are typically applied and difficulties with routing completion often occur. Finally, when nets violate crosstalk specifications, which they generally do, designers have no choice but to locally ‘fix’ those nets manually, one net at a time. Buffers and repeaters are often inserted, drivers are resized, wires' width and spacing are modified, and parallelism is minimized.
Post-routing algorithms to minimize crosstalk violations have been studied extensively in the scientific literature. They can be classified into rules that attempt to decrease crosstalk by changing the spacing between the interconnecting wires, and rules that attempt to decrease crosstalk by changing the adjacencies among the interconnecting wires. Both of these rule classes suffer from severe limitations. First, even though spacing is a two-dimensional problem, it is usually carried out as two independent, one-dimensional steps. Vertical coupling is accounted for by introducing a penalty function to make sure that the final crosstalk will not exceed the initial crosstalk. Second, current spacing algorithms adjust positions of the interconnecting wires locally within routing region, not globally within the entire routing area of an IC. Third, it has been noted that the non-linearity of the objective functions involving crosstalk makes it difficult to develop efficient algorithms for their optimization. Furthermore, crosstalk for interconnecting wires that are placed into final positions early in the routing process is computed using estimations for coupling with neighboring wires that have not yet been placed. Iterative rip-up and reroute may be used to remedy this problem. However, depending on when rip-up and reroute is performed during the routing process, routing space may or may not be available, and rip-up may be so extensive that a complete re-route becomes necessary. Although in general, post-routing optimization is less flexible in moving the interconnecting wires around than during detail routing, it is still the best way to reduce coupling capacitances and hence crosstalk between the interconnecting wires for a general layout problem.